Job Description

Senior FPGA Design Engineer

Ref No: AM17646

County Dublin, Republic of Ireland

Competitive salary

Senior FPGA Design Engineer - Dublin.

In this role you will be responsible for:

• Design of FPGA systems for radio communication systems including digital front-end DSP such as filters, up and down-conversion, DPD, CFR.
• Active collaboration with a multidisciplinary team on architecture and design with digital design expertise. Provide inputs to architecture and design reviews.
• Multi-gigabit interface design (Ethernet, SGMII, RGMII, PCI).
• Design documentation including product specifications, design descriptions, and test specifications.
• Systemization of a digital ASIC (FPGA, ARM, SoC, IP Cores).
• Write, simulate, and verify Verilog/SystemVerilog based FPGA designs.
• Developing API and Software for FPGA bring-up and system-level validation and operation.
• SoC performance and power estimation and optimization, clock, and reset distribution optimization.
• Device Evaluation, Schematic Entry, PCB Layout support, and review.
• Design for Manufacturability, Quality, Cost & Test.
• Support of New Product Introduction to Manufacture.

Interested applicants should have experience of:

O-RAN and C-RAN knowledge is a must.
• Strong knowledge of FPGA tool flows; Synthesis, Partitioning, Place & Route: Xilinx Vivado HLx and Intel FPGA Quartus Prime Standard/Pro Edition.
• Knowledge of multi-gigabit interface protocols (Ethernet, SGMII, RGMII), memory technologies (DDR3, DDR4), interconnect protocols (PCIe), digital logics, and common communication interfaces (UART, USB, SPI, I2C).
• Skilled in digital frontend design (DSP, CFR, DPD, Up and Down Converters, Digital Filters).
• Familiarity with logic synthesis, verification, timing closure, and physical design principles.
• Electronic Circuit & System Design Fundamentals including analog, digital, and power.
• Knowledge of FPGA/ARM and IP Cores systemization.
• Circuit and System Simulation (Matlab, PSpice) Competence.
• Proficient with scripting languages such as Tcl or Python, and programming languages such as C/C++ including low-level programming (firmware) of complex computer systems and mixing HDL with C/C++ for simulation purposes.
• Knowledge of SystemC (IEEE 1666-2011), UVM (IEEE 1800.2-2017) and/or SystemC-AMS (IEEE 1666.1-2016) is a plus.
• Detailed knowledge of laboratory measurements using equipment such as Oscilloscope, Signal Generator, Signal Analyser.
• Familiar with Agile Project Management.
• You must have experience with tools such as SVN, Git, and familiarity with 1588 and SyncE standards.

A minimum of 5 years' experience, with Bachelor’s degree in Electronic / Electrical / Telecommunication Engineering. A Master’s Degree or Ph.D. with relevant emphasis is advantageous