Ref No: AM16584y
SENIOR HARDWARE FPGA DESIGN ENGINEER - Poland (Gdynia)..
Our client seeks a Senior Hardware Design Engineer with outstanding FPGA development skills, who will be responsible for definition and architecture of leading-edge board-level Remote Radio Unit systems.
The role spans the full development life-cycle through specification, design, documentation, implementation, debug and test.
The established team working environment provides an opportunity to develop and grow skills and expertise in embedded system hardware development for leading edge wireless technologies.
Desired Skills and Expertise:
A Bachelor’s Degree in Electronic or Computer Engineering or other relevant discipline and at least 5 years' relevant experience is required.
It is expected that candidates will have demonstrated some or all of the following competencies.
• 5+ years' experience at system architect level for FPGA/ARM based designs.
• Systemisation of a digital ASIC (FPGA, ARM, SoC).
• Knowledge of FPGA/ARM and IP Cores systemisation.
• Understanding of hardware, firmware, and software/hardware interactions.
• Knowledge of multi-gigabit interface protocols (Ethernet, SGMII, RGMII), memory technologies (DDR3, DDR4), interconnect protocols (PCIe), digital logics and common communication interfaces (UART, USB, SPI, I2C) is highly desired.
• Experience in digital frontend design (DSP, CFR, DPD, Up and Down Converters, Digital Filters).
• Experience in SoC performance and power estimation and optimization, clock and reset distribution optimization.
• Work with internal and external partners to bring reference designs to production.
• Experience working with Xilinx Zynq-7000 and/or Intel Arria-V SoC is a plus.
• Knowledge of RF radio transceiver is a plus.
• Active collaboration with multi-disciplinary team on architecture and design within digital design expertise. Provide inputs to architecture and design reviews.
• Ability to work effectively with multi-disciplinary engineering team is essential.
• At least 5 years' hands-on Verilog and/or SystemVerilog experience.
• Experience with scripting languages such as Tcl or Python
• Experience with programming languages such as C/C++ including low-level programming (firmware) of complex computer systems and mixing HDL with C/C++ for simulation purpose.
• Strong knowledge of FPGA tool flows; Synthesis, Partitioning, Place & Route: Xilinx Vivado HLx and Intel FPGA Quartus Prime Standard/Pro Edition.
• Be familiar with software development process: source version control tools (Git), unit tests (TDD), code review, refactoring, automate builds (CMake), continuous integration (CI) and continuous deployment (CD).
• Experience in logic synthesis, verification, timing closure, and physical design principles.
• Experience with highly pipelined designs, and with multiple-clock-domain designs
• Knowledge of SystemC (IEEE 1666-2011), UVM (IEEE 1800.2-2017) and/or SystemC-AMS (IEEE 1666.1-2016) is a plus